Gbólólólóhùn Asiri: Asiri rẹ ṣe pataki pupọ si wa. Ile-iṣẹ wa ṣe ileri lati ṣe sọ alaye ti ara ẹni si eyikeyi ifihan pẹlu awọn igbanilaaye rẹ.
Aṣeṣe No.: NSO4GU3AB
Iṣowo: Ocean,Air,Express,Land
Iru owo sisan: L/C,T/T,D/A
Incoterm: FOB,EXW,CIF
4GB 1600mHz 240-PIN DDR3 UDImm
Itan atunyẹwo
Revision No. |
History |
Draft Date |
Remark |
1.0 |
Initial Release |
Apr. 2022 |
|
Pabo tabili tabili
Model |
Density |
Speed |
Organization |
Component Composition |
NS04GU3AB |
4GB |
1600MHz |
512Mx64bit |
DDR3 256Mx8 *16 |
Isapejuwe
Hengstar ko ko dẹkun DDR3 Sdram Stram (ti a ko fi agbara silẹ Double Meji awọn modulu iranti ni ila-giga) awọn modulu iranti DDR3 ti o lo awọn ẹrọ SDR3. NS04Gab jẹ 512m X 64-bit meji-bi bit meji drrd3-1600 C11 1.5V SDRMA DRRUM SCRAM, ti o da lori awọn paati mẹrinla 256m x 8-bit Fbga. SPD ti ṣe agbekalẹ si Jedec Boṣewa DDR3-1600 Akoko ti 11-11-11-11-11-11 ni 1.5V. Kọọkan 30-bamm n lo awọn ika ọwọ awọn olubasọrọ goolu. Srdram ko ṣee ṣe Dipọmm ti pinnu fun lilo bi iranti akọkọ nigbati a fi sori ẹrọ ni awọn eto bii awọn PC ati awọn iṣẹ.
Awọn ẹya
Ipese agbara: VDD = 1.5V (1.425v si 1.575v)
vdq = 1.5V (1.425v si 1.575v)
800MHz FCK fun 1600MB / iṣẹju-aaya / Pin
8 ominira banki
AKIYESI rocrogramations Stprogragrammable: 11, 10, 9, 8, 7, 6, 6, 6, 6
prography Admic Admidict: 0, CL - 2, tabi CL - 1 Aago
8-bit de-ri
Akoko ipari: 8 (interloveseeve laisi eyikeyi opin, leralera pẹlu adirẹsi "000" nikan), 4 pẹlu TcCD laipe
-itọsọna data
ternal (ti ara) ijuwe; Isamisi ara ẹni ti inu nipasẹ ZQ PIN (RZQ: 240 Ohm ± 1%)
on ku ifopinsi lilo PIN PIN
arage akoko 7.8us ni isalẹ ju TUS 85 ° C, 3.9us ni 85 ° C <T
Tun atunto Tun
Agbara awakọ data ti iṣelọpọ data
O ly-nipasẹ torology
pcb: iga 1.18 "(30mm)
Awọn ifarahan roo ati halogen-free
Awọn ọna kika akoko
MT/s |
tRCD(ns) |
tRP(ns) |
tRC(ns) |
CL-tRCD-tRP |
DDR3-1600 |
13.125 |
13.125 |
48.125 |
2011/11/11 |
Tabili adirẹsi
Configuration |
Refresh count |
Row address |
Device bank address |
Device configuration |
Column Address |
Module rank address |
4GB |
8K |
32K A[14:0] |
8 BA[2:0] |
2Gb (256 Meg x 8) |
1K A[9:0] |
2 S#[1:0] |
Awọn apejuwe PIN
Symbol |
Type |
Description |
Ax |
Input |
Address inputs: Provide the row address for ACTIVE commands, and the column |
BAx |
Input |
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or |
CKx, |
Input |
Clock: Differential clock inputs. All control, command, and address input signals are |
CKEx |
Input |
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry |
DMx |
Input |
Data mask (x8 devices only): DM is an input mask signal for write data. Input data is |
ODTx |
Input |
On-die termination: Enables (registered HIGH) and disables (registered LOW) |
Par_In |
Input |
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. |
RAS#, |
Input |
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being |
RESET# |
Input |
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and |
Sx# |
Input |
Chip select: Enables (registered LOW) and disables (registered HIGH) the command |
SAx |
Input |
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address |
SCL |
Input |
Serial |
CBx |
I/O |
Check bits: Used for system error detection and correction. |
DQx |
I/O |
Data input/output: Bidirectional data bus. |
DQSx, |
I/O |
Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; |
SDA |
I/O |
Serial |
TDQSx, |
Output |
Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD |
Err_Out# |
Output (open |
Parity error output: Parity error found on the command and address bus. |
EVENT# |
Output (open |
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical |
VDD |
Supply |
Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The |
VDDSPD |
Supply |
Temperature sensor/SPD EEPROM power supply: 3.0–3.6V. |
VREFCA |
Supply |
Reference voltage: Control, command, and address VDD/2. |
VREFDQ |
Supply |
Reference voltage: DQ, DM VDD/2. |
VSS |
Supply |
Ground. |
VTT |
Supply |
Termination voltage: Used for control, command, and address VDD/2. |
NC |
– |
No connect: These pins are not connected on the module. |
NF |
– |
No function: These pins are connected within the module, but provide no functionality. |
Awọn akọsilẹ : Tabili Apejuwe PIN ni isalẹ jẹ atokọ okeerẹ ti gbogbo awọn pinni ti o ṣeeṣe fun gbogbo awọn modulu DDR3. Gbogbo awọn pinni ti a ṣe akojọ le Ko ni atilẹyin lori module yii. Wo awọn iṣẹ iyansilẹ fun alaye ni pato si module yii.
Ṣiṣẹpọ Iṣeduro Iṣeduro Iṣẹ
4GB, 512mx64 module (2ran ti x8)
Awọn iwọn module
Ifiranṣẹ iwaju
Ifiranṣẹ iwaju
Awọn akọsilẹ:
Awọn iwọn 1.Lill wa ni milimita (awọn inṣis); Max / min tabi aṣoju (tẹ) ti ko ṣe akiyesi.
2. Ulelerice lori gbogbo awọn iwọn ± 0.15mm ayafi ti bibẹẹkọ ti pàtó kan.
3. Nagram onisopọ jẹ fun itọkasi nikan.
Ọja Isori : Awọn ẹya ẹrọ Smart Clam ile-iṣẹ
Gbólólólóhùn Asiri: Asiri rẹ ṣe pataki pupọ si wa. Ile-iṣẹ wa ṣe ileri lati ṣe sọ alaye ti ara ẹni si eyikeyi ifihan pẹlu awọn igbanilaaye rẹ.
Fọwọsi alaye diẹ sii ki o le wọle si ọ ni iyara
Gbólólólóhùn Asiri: Asiri rẹ ṣe pataki pupọ si wa. Ile-iṣẹ wa ṣe ileri lati ṣe sọ alaye ti ara ẹni si eyikeyi ifihan pẹlu awọn igbanilaaye rẹ.